IEEE Spectrum: Taiwan's Tiny RRAM- Island engineers to demonstrate next-generation memory in its smallest footprint yet

Publication

A.         Journals

2005

1.           Kung-Hong Lee; Ya-Chin King, “High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications”, Japanese Journal of Applied Physics, vol. 44, no 1A, January, 2005:44-49

2.           Kung-Hong Lee; Meng-Yi Wu, Sen-Hue Dai, Ya-Chin King, “ Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture”, Japanese Journal of Applied Physics, vol. 44, no 4B, April, 2005: 2083-2087

3.           Cheng-Hsiao Lai, Yueh-Ping Yu; Kung-Hong Lee; Ya-Chin King, “A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors”, Japanese Journal of Applied Physics, vol. 44, no 4B, April, 2005: 2214-2216

4.           Wei-Cheng Lin; Tsung-Chien Wu; Yi-Hung Tsai; Long-Jei Du; Ya-Chin King; “Reliability evaluation of class-E and class-a power amplifiers with nanoscaled CMOS technology”, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005: Page(s):1478-1483

5.           Ling-Chang Hu, An-Chi Kang*, T.I. Wu*, Eric Chen*, J.R. Shih*, H.W. Chin*, Yao-Feng Lin*, Kenneth Wu*, Ya-Chin King, “Gate stress effect on low temperature data retention characteristics of split-gate flash memories”, Microelectronics Reliability, Volume: 45, Issue: 9-11, Sep.-Nov. 2005: 1331-1336

6.           Kung-Hong Lee, Shih-Cheng Wang, Ya-Chin King, “Self-convergent scheme for logic-process-based multilevel/analog memory”, IEEE Transactions on Electron Devices, Volume 52, Issue 12, December 2005: Page(s):2676-2681

7.           Ying-Chieh Chuang; Shih-Fang Chen; Shi-Yu Huang; Ya-Chin King; “Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion”, IEEE Transactions on Consumer Electronics, Volume 51, Issue 4, Nov. 2005 Page(s):1212-1217

8.           Y.H. Wang, M.C. Wu, C.J. Lin, W.T. Chu, Y.T. Lin, Chung S. Wang, and K. Y. Cheng, “An Analytical Programming Model for the Drain Coupling Source Side Injection Split Gate Flash EEPROM”, IEEE Trans. on Electron Device (ED), Volume 52, Issue 3, pp.385-391 March 2005. :2.052

2006

9.           Y.H. Wang, C.J. Lin, W.T. Chu, Y.T. Lin, C. Wang, and M. C. Wu, “On the dynamic coupling ratio of drain-coupling split gate Flash using quasi-two dimensional analysis”, IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS Vol153 (2) Pages: 115-123, APR, 2006

10.       Wu MY; Dai SH; Hu SF; E.C.-S.; Hsu, C.C.-H.; King, Y.-C., “Highly scalable ballistic injection AND-type (BiAND) flash memory”, IEEE Transactions on Electron Devices, 53(1): 109-111, Jan 2006

11.       Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; “Interconnect Capacitance Characterization Using Charge-Injection-Induced Error-Free (CIEF) Charge-Based Capacitance Measurement (CBCM)”, IEEE Transactions on Semiconductor Manufacturing, 19(1): 50-56 FEB 2006

12.       Wu MY; Dai SH; Hu SF; Yang, E.C.-S.; Hsu, C.C.-H.; King YC; “Comprehensively study on a ballistic-injection AND-type flash memory cell”, Japanese Journal of Applied Physics, 45(2A): 674-679 FEB. 2006

13.       Lai CH, King YC, Huang SY, “A 1.2-V 0.25um clock output pixel architecture with wide dynamic range and self-offset cancellation”, IEEE SENSORS JOURNAL 6 (2): 398-405 APR 2006

14.       Hsieh SI, Chen HT, Chen YC, Chen CL, King YC. “MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs” IEEE ELECTRON DEVICE LETTERS 27 (4): 272-274 APR 2006

15.       Hu LC, Kang AC, Shih JR, Lin YF, Wu K, King YC, “Statistical modeling for postcycling data retention of split-gate flash memories”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 6 (1): 60-66 MAR 2006

16.       Chang YW, Chang HW, Lu TC, King YC, Ting WC, Ku YHJ, Lu CY, “Charge-based capacitance measurement for bias-dependent capacitance”, IEEE ELECTRON DEVICE LETTERS 27 (5): 390-392 MAY 2006

17.       Lai CH, Lai LW, Chiang WJ, King YC, “A logarithmic response complementary metal oxide semiconductor image sensor with parasitic P-N-P bipolar junction transistor”, JAPANESE JOURNAL OF APPLIED PHYSICS 45 (4B): 3251-3255 APR 2006

18.       Hsieh SI, Chen HT, Chen YC, Chen CL, Lin JX, King YC, “Reliability and memory characteristics of sequential laterally solidified low temperature polycrystalline silicon thin film transistors with an oxide-nitride-oxide stack gate dielectric”, JAPANESE JOURNAL OF APPLIED PHYSICS 45 (4B): 3154-3158 APR 2006

19.       Wu MY, Dai SH, Lee KH, Hu SF, King YC, “ Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memory”, SOLID-STATE ELECTRONICS 50 (3): 309-315 MAR 2006

20.       Hsieh SI, Chen HT, Chen YC, Chen CL, King YC, “Threshold voltage uniformity enhancement for low-temperature polysilicon thin-film transistors using tilt alignment technique”, ELECTROCHEMICAL AND SOLID STATE LETTERS 9 (7): H57-H60 2006

21.       Chen HT, Chen YC, Lin JX, Hsieh SI, King YC, “Roughness effect on uniformity and reliability of sequential lateral solidified low-temperature polycrystalline silicon thin-film transistor”, ELECTROCHEMICAL AND SOLID STATE LETTERS 9 (8): H81-H83 2006

22.       Hu, L. C., Kang, A. C., Wu, T. Y., Shih, J. R., Lin, Y. F., Wu, K. and King, Y. C. “Efficient Low-Temperature Data Retention Lifetime Prediction for Split-Gate Flash Memories Using a Voltage Acceleration Methodology”, IEEE Transactions On Device And Materials Reliability 6(4): 528-533 SEP 2006

23.       Y.H. Wang, C.J. Lin, W.T. Chu, Y.T. Lin, C. Wang, and M. C. Wu, “On Application of Analytical Model for Drain-coupling Split Gate Flash: An Analytical Solution to Source-Side Injection Multilevel Programming”, Jpn. J. Appl. Phys. (JJAP), Vol.45, No. 3, pp.L77-L79, 2006. :1.222

2007

24.       Lu S.C., Wu, Z. H., Huang C. E., Hung S. J., Chen M. H., King Y. C. “CMOS micromachined grippers with on-chip optical detection”, Journal of Micromechanics and Microengineering 17(2): 482-488 FEB 2007

25.       Cao X., Chiang W. J., King Y. C., Lee Y. K. “Electromagnetic Energy Harvesting Circuit With Feedforward and Feedback DC-DC PWM Boost Converter for Vibration Power Generator System”, IEEE Transactions On Power Electronics 22(2) 679-685 MAR 2007

26.       Chiang W. J., Chen H. C., King Y. C. “A New Photodiode Model for SPICE Simulation of Complementary Metal-Oxide-Semiconductor Image Sensors”, JAPANESE JOURNAL OF APPLIED PHYSICS 46 (4B): 2352-2359 APR 2007

27.       Hsieh S. I., Liang H. Y. , Lin C. J., King Y. C., “Stress-induced width-dependent degradation of low-temperature polycrystalline silicon thin-film transistor”, APPLIED PHYSICS LETTERS 90, 183502 APR 2007

28.       Hsu T. H. Lue H. T., King Y.C., Hsieh J. Y., Lai E.K., Hsieh K. Y., Liu R., Lu C. Y. “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-Type Flash Memory”, IEEE ELECTRON DEVICE LETTERS 28 (5): 443-445 MAY 2007

29.       Chen H. T., Hsieh S. I., Lin C. J., King Y. C., “Embedded TFT NAND-Type Nonvolatile Memory in Panel”, IEEE ELECTRON DEVICE LETTERS 28 (6): 499-501 JUNE 2007

30.       Chiang WJ, Chen CY, Lin CJ, King Y.C., “Silicon nanocrystal-based photosensor on low-temperature polycrystalline-silicon panels”, APPLIED PHYSICS LETTERS 91 (5)051120 APR 2007

31.       Liaw CW, Chang CH, Lin MJ, King Y.C ,Hsu CCH, Lin CJ, “P-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor with split N-type buried layer for high breakdown voltage and low specific on-resistance”, JAPANESE JOURNAL OF APPLIED PHYSICS 46 (7A): 4046-4049 JUL 2007

32.       Lai HC, Cheng KY, King YC, Lin CJ, “A 0.26-µm2 U-Shaped nitride-based programming cell on pure 90-nm CMOS technology”, IEEE ELECTRON DEVICE LETTERS 28 (9): 837-839 SEP 2007

33.       Chen CF, Huang SY, King YC, “Built-in self-repair for die-to-die misalignment of multidie space sensors”, IEEE SENSOR JOURNAL Vol.7, No.9, 1354-1355 SEP 2007

34.       Hsu TH, King YC, Wu JY, Shih YH, Lue HT, A novel channel-program-erase technique with substrate transient hot carrier injection for SONOSNAND flash application”; SOLID-STATE ELECTRONICS 51 (11-12), 1523-1528 NOV-DEC 2007

35.       Chorng-Wei3 Liaw, Leaf Yeh, Ming-Jang Lin, and Chrong Jung Lin, ”Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor”, IEEE ELECTRON DEVICE LETTERS (EDL), VOL. 28, NO. 8, 737-739, JUNE 2007. :2.716

2008

36.       Dai SH, Lin CJ, King YC, “Leakage suppression of low-voltage transient voltage suppressor”, IEEE TRANSACTIONS ON ELECTRON DEVICES Volume: 55 Issue: 1 Pages: 206-210 Published: JAN 2008

37.       Chen M, Huang CE, Tseng YH, King YCA new antifuse cell with programmable contact for advance CMOS logic circuits”, IEEE ELECTRON DEVICE LETTERS Volume: 29 Issue: 5 Pages: 522-524 Published: MAY 2008

38.       Chen CY, Wang JJ, Lin CJ, King YC, “Real-time variable-resolution complementary metal-oxide-semiconductor field-effect transistors image sensor”, JAPANESE JOURNAL OF APPLIED PHYSICS Volume: 47 Issue: 4 Pages: 2756-2760 Part: Part 2 Published: APR 2008

39.       Chang YW, Chang HW, Lu TC, King YC, “Combining a novel charge-based capacitance measurement (CBCM) technique and split C-V method to specifically characterize the STI stress effect along the width direction of MOSFET devices”, IEEE ELECTRON DEVICE LETTERS Volume: 29 Issue: 6 Pages: 641-644 Published: JUN 2008

40.       Chen YJ, Huang CE, Chen HM, King YC, “A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology”, IEEE ELECTRON DEVICE LETTERS Volume: 29 Issue: 8 Pages: 938-940 Published: AUG 2008

41.       Lee TY, Chiu CC, Liu YC, King YC, “A new embedded one-time-programmable MNOS memory fully compatible to LTPS fabrication for system-on-panel (SOP) applications”, IEEE ELECTRON DEVICE LETTERS Volume: 29 Issue: 8 Pages: 906-908 Published: AUG 2008

42.       Lai HC, Huang CE, King YC, Lin CJ, “Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal-Oxide-Semiconductor Logic Technology”, JAPANESE JOURNAL OF APPLIED PHYSICS Volume: 47 Issue: 11 Pages: 8369-8374, NOV 2008

43.       Hung-Sheng Shih, Shang-Wei Fang, An-Chi Kang, Ya-Chin King, and Chrong-Jung Lin, “High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory APPLIED PHYSICS LETTERS Volume: 93 Issue: 21 Article Number: 213503 , NOV 24 2008

44.       Liaw CW, Yeh L, Lin MJ, Lin CJ, “Trench termination design and analysis in low-voltage N-channel trench power metal-oxide-semiconductor field-effect transistor JAPANESE JOURNAL OF APPLIED PHYSICS Volume: 47 Issue: 3 Pages: 1507-1511 MAR 2008

2009

45.       Wen-Jen Chiang; Chrong-Jung Lin; Ya-Chin King; An-Thung Cho; Chia-Tien Peng; Wei-Ming Huang; “Integrated Ambient Light Sensor With Nanocrystalline Silicon on a Low-Temperature Polysilicon Display Panel” Electron Devices, IEEE Transactions on Volume 56, Issue 4, Page: 578-586, April 2009

46.       Wen-Jen Chiang; Chrong-Jung Lin; Ya-Chin King; An-Thung Cho; Chia-Tien Peng; Wei-Ming Huang; “Integrated Ambient Light Sensor With Nanocrystalline Silicon on a Low-Temperature Polysilicon Display Panel” Electron Devices, IEEE Transactions on Volume 56, Issue 4, Page: 578-586, April 2009

47.        Wen-Jen Chiang,z Chrong-Jung Lin, and Ya-Chin King, “Embedded Optical Sensor Using Gate-Body-Tied Thin-Film Transistor on Low-Temperature Poly-Silicon Display Panel”, Electrochemical and Solid-State Letters, 12( 5) J51-J53 (2009)

48.      Sheng-Huei Dai*, Jeng-Jie Peng, Chia-Cheng Chen, Chrong-Jung Lin, and Ya-Chin King, “Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process” , Japanese Journal of Applied Physics 48 (2009) 04C082

49.      Yi-Hung Tsai *, Kai-Chun Lin, Hsin-Yi Chiu, Hung-Sheng Shih, Ya-Chin King, Chrong Jung Lin, “A study of gateless OTP cell using a 45 nm CMOS compatible process” , Solid-State Electronics SSE 5275 No. of Pages 7, Model 5G, Volume: 53 Issue: 10 Pages: 1092-1098 Published: 2009

50.       Tsai, Yi-Hung, Lin, Kai-Chun, Kuo, Cheng-Hsiung, Chih, Yue-Der, Lin, Chrong-Jung, King, Ya-Chin, “A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate”, IEEE ELECTRON DEVICE LETTERS   Volume: 30   Issue: 10   Pages: 1090-1092   Published: 2009

51.      Chia-En Huang, Ying-Je Chen, Han-Chao Lai, Ya-Chin King, and Chrong Jung Lin, “A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process”, IEEE TRANSACTIONS ON ELECTRON DEVICES   Volume: 56   Issue: 6   Pages: 1228-1234   Published: 2009

52.      Tzu-Hsuan Hsu, Hang-Ting Lue, Ya-Chin King, Yi-Hsuan Hsiao, Sheng-Chih Lai, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, “Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices”,IEEE TRANSACTIONS ON ELECTRON DEVICES Volume: 56   Issue: 6   Pages: 1235-1242   Published: 2009

53.      Chih-Yang Chen, Chien-Yu Huang, Chrong-Jung Lin and Ya-Chin King “A low-temperature polycrystalline-silicon thin-film transistor micro-manipulation array with indium tin oxide micro-coils and real-time detection” JOURNAL OF MICROMECHANICS AND MICROENGINEERING J. Micromech. Microeng. 19 (2009) 125023(5pp)

2010

54.       Yi-Hung Tsai, Hsiao-Lan Yang, Wun-Jie Lin, Chrong Jung Lin*, and Ya-Chin King, “A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell”, Japanese Journal of Applied Physics 49 (2010) 04DD13:1.138

55.       Chia-En Huang, Yuan Heng Tseng, Cheng-Hsiung Kuo1, Yu-De Chih1, Ya-Chin King, and Chrong Jung Lin*, “Multilevel Antifuse Cells with Programmable Contact in Pure 90nm logic Process”, Japanese Journal of Applied Physics 49 (2010) 014202:1.138

56.      Chih-Yang Chen, Chrong-Jung Lin, and Ya-Chin King, “Integration of Microcoil Magnetic Manipulation with High-Sensitivity Complementary Metal–Oxide–Semiconductor Photosensor Detection in Bio-Analyses”, Japanese Journal of Applied Physics 49 (2010) 04DL06:1.138

57.      Sheng-Huei Dai_, Jeng-Jie Peng, Chia-Cheng Chen, Chrong-Jung Lin, and Ya-Chin King, “Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor”, Japanese Journal of Applied Physics 49 (2010) 04DP13:1.138

58.     Te-Yu Lee, Chrong Jung Lin, Ya-Chin King, “High-uniformity 2T1C AMOLED panels by a built-in trimming method”, Journal of the Society for Information Display August 2010 -- Volume 18, Issue 8, pp. 544-549

 

B.     Conference Papers

2005

1.           Chen HT, Hsieh SI, Chen YC, Tsai PH, Chen CL, Huang CJ, Lin JX, Chang CJ, King YC. “Novel flash memory structure using sequential lateral solidified low temperature poly-Si technology”. IDW/AD'05 - Proceedings of the 12th International Display Workshops in Conjunction with Asia Display 2005; 2005; Takamatsu, Japan

2.           Wu M-Y, Feng S-C, King Y-C. “A novel single poly-silicon EEROM using trench floating gate”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan

3.           Hu L-C, Kang A-C, Wu TI, Chen E, Shih JR, Chin HW, Lin Y-F, Wu K, King Y-C. “A voltage acceleration lifetime model to predict post-cycling LTDR characteristics of split-gate flash memories”. IEEE International Reliability Physics Symposium Proceedings; 2005; San Jose, CA, United States

4.           Chang YW, Chang HW, Lu TC, King Y, Ting W, Ku J, Lu CY. “A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance”. IEEE International Conference on Microelectronic Test Structures; 2005; Leuven, Belgium.

5.           Lee K-H, Wang S-C, King Y-C. “Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan

6.           Lai C-H, King Y-C, Huang S-Y. “A 1.2V 0.25-μm clock output pixel sensor with wide dynamic range”. Proceedings of SPIE - The International Society for Optical Engineering; 2005; San Jose, CA, United States

7.           Ssu-I Hsieh and Ya-Chin King, “Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric”, Proceeding for the 2005 International Conference on Solid State Devices and Materials, Tokyo, Japan

8.           Cheng-Hsiao, Liang-Wei Lai, and Ya-Chin King, “A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT”, Proceeding for the 2005 International Conference on Solid State Devices and Materials, pp. 940-941 Tokyo, Japan

9.           Wei-Cheng Lin and Ya-Chin King, “Reliability Evaluation of 5.2GHz CMOS Receiver”, European Microwave Conference, France, October 2005

2006

10.       W. J. Chiang, H. C. Chen and Y. C. King, “Photodiode Model for CMOS Image Sensor SPICE Simulation”, International Conference on Solid State Devices and Materials, Tokyo, Japan, September 2006

11.       Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, Hsieh KY, Liu R, Lu CY, “A novel channel-program-erase technique with substrate transient hot carrier injection for SONOS memory application 36th European Solid-State Device Research Conference Pages: 222-225, 2006

12.       Lu MSC, Huang CE, Wu ZH, Chen CF, Huang SY, King YC, “A CMOS micromachined gripper array with on-chip optical detection”, 2006 IEEE Sensors, Vols 1-3 Pages: 37-40, 2006

2007

13.       Sheng-Huei Dai, Hai-Ning Wang*, Ming-Tai Chiang*, Chrong-Jung Lin, and Ya-Chin King, “Leakage Suppression Of Low Voltage Transient Voltage Suppressor”, IEEE International Reliability Physics Symposium Proceedings; Phoenix , AZ, United States, April 2007

14.      Hsing-Yi Liang, Szu-I Hsieh, Hung-Tse Chen*, Chrong-Jung Lin, Ya-Chin King, “Degradation Dependent on Channel Width in Sequential Lateral Solidified Poly-Si Thin Film Transistors”, IEEE International Reliability Physics Symposium Proceedings; Phoenix , AZ, United States, April 2007

15.      Wang JJ, Lin CJ, King YC, “Real-time variable-resolution complementary metal-oxide-semiconductor field-effect transistors image sensor”, International Conference on Solid State Devices and Materials, Tokyo, Japan, September 2007

16.       Chia-En Huang, Hsin-Ming Chen, May-Be Chen, Ya-Chin King, Chrong-Jung Lin, “A New CMOS Logic Anti-Fuse Cell with Programmable Contact”, IEEE 22nd IEEE Nonvolatile Semiconductor Memory Workshop (NVSMW), 2007, pp.48-51.

17.       Wen-Jen Chiang, An-Thung Cho, Chia-Tien Peng, Chih-Wei Chao, Kun-Chih Lin, and Feng-Yuan Gan, Chih-Yang Chen, Chrong-Jung Lin, and Ya-Chin King, “Silicon Nanocrystals Photo Sensor Integrated on Low-Temperature Polycrystalline-Silicon Panels”, 2007 International Society for Display Information (SID), 2007, pp.294-297.

18.       An-Thung Cho , Chia-Tien Peng, Wen-Jen Chiang, Chrong-Jung Lin, Chih-Wei Chao, Kun-Chih Lin, Ya-Chin King, Chien-Sen Weng, and Feng-Yuan Gan, “Integrated Ambient Light Sensor in LTPS LCD panel with Silicon nanocrystals photosensor”, The 14th International Display Workshops (IDW), 2007, pp.103-106.

19.       Chia-En Huang, Hsin-Ming Chen, Han-Chao Lai, Ying-Je Chen, Ya-Chin King, Chrong Jung Lin, “A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process”, IEEE International Electron Device Meeting (IEDM), 2007, pp.91-94.

20.       Jian-Jie Wang, Chrong-Jung Lin and Ya-Chin King, “Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor”, International Conference on Solid State Devices and Materials (SSDM), 2007.

21.       Chung-Wei Chang, Shou-Gwo Wuu, Dun-Nian Yaung, Chien-Hsien Tseng, Han-Chi Liu, David Yen, Yi-Jiun Lin, Chun-Ming Su, Chun-Yao Ko, C.Y. Yu, C.H. Lo, F.J.Hsiu, C.S.Tsai, Chung S. Wang, Mingo Liu, Chrong-Jung Lin, Ya-Chin King, “High Sensitivity of Dielectric films Structure for Advanced CMOS Image Sensor Technology”, IEEE International Image Sensor Workshop (IISW), 2007

22.       Yi-Hung Tsai, Hsin-Ming Chen*, Hsin-Yi Chiu, Hung-Sheng Shih, Han-Chao Lai, Ya-Chin King, and Chrong Jung Lin “45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process”, IEEE International Electron Device Meeting (IEDM), 2007, pp.95-98.

23.       Hisu TH, Lue HT, Lai EK, Hsieh JY, Wang SY, Yang LW, King YC, Yang T, Chen KC, Hsieh KY, Liu R, Lu CY, “A high-speed BE-SONOS NAND Flash utilizing the field-enhancement effect of FinFET”, IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 913-916 2007

2008

24.       Sheng-Huei Dai, Chrong-Jung Lin, and Ya-Chin King, “Low Voltage Transient Voltage Suppressor with V-Groove Structure”, IEEE 46th Annual International Reliability Physics Symposium (IRPS), 2008

25.       Sheng-Huei Dai, Jeng-Jie Peng, Chia-Cheng Chen, Chrong-Jung Lin, and Ya-Chin King, “Low-Capacitance Low-Voltage Transient Voltage Suppression Circuit by Diode activated SiGe HBT in SiGe HBT BiCMOS Process”, International Conference on Solid State Devices and Materials, Tsukuba, 2008, pp. 314-315

26.       Wen-Jen Chiang, Chrong-Jung Lin, Ya-Chin King, An-Thung Cho, Chia-Tien Peng, Chih-Wei Chao, Kun-Chih Lin, Feng-Yuan Gan, “Silicon-nanocrystal-based photosensor integrated on low-temperature polysilicon panels”, 2008 Journal of the Society for Information Display

27.       Hsu TH, Lue HT, Peng WC, Tsai CH, King YC, Wang SY, Wu MT, Hong SP, Hsieh JY, Yang LW, Lian NT, Yang T, Chen KC, Hsieh KY, Liu R, Lu CY, “A study of sub-40nm FinFET BE-SONOS NAND flash”, IEEE Non-Volatile Semiconductor Memory Workshop/3rd International Conference on Memory Technology and Design, Pages: 115-116, 2008

28.       Hsu TH, Lue HT, Peng WC, King YC, Wu CW, Wang SY, Wu MT, Hong SP, Hsieh JY, Yang T, Chen KC, Hsieh KY, Liu R, Lu CY, “A High performance and scalable FinFET BE-SONOS device for NAND Flash memory application”, International Symposium on VLSI Technology, Systems and Applications, Pages: 56-57, 2008

2009

29.    Chia-Cheng Chen, Sheng-Huei Dai, Jeng-Jie Peng, Chrong-Jung Lin, and Ya-Chin King, “Lateral Back-to-back-diode for Low-Capacitance Transient Voltage Suppressor” International Conference on Solid State Devices and Materials, Sendai, 2009pp1244-1245

30.    Hsun OuYang, Ying-Je Chen, Chia-En Hung and Chrong-Jung Lin, “Source-Side Injection Programmed P-channel Self-Aligned-Nitride OTP Cell for 90nm Logic Nonvolatile Memory Applications”, International Conference on Solid State Devices and Materials, Sendai, 2009, pp434-435

31.    Yuan Heng Tseng1, Chia-En Huang1, C. -H. Kuo2, Y. -D. CHih2, Chrong Jung Lin1 “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, IEEE International Electron Devices Meeting (IEDM), Baltimore 2009

32.    Chih-Yang Chen, Chien-Yu Huang, Chrong-Jung Lin and Ya-Chin King, “Integration Module of Microcoil Magnetic Manipulation with High Sensitivity CMOS Photosensor Detection in Bio-Analyses” International Conference on Solid State Devices and Materials, Sendai, 2009

33.   Yi-Hung Tsai, Hsiao-Lan Yang, Wun-Jie Lin, Chrong Jung Lin, and Ya-Chin King, “A New Differential Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell” International Conference on Solid State Devices and Materials, Sendai, 2009

2010

34.    Yuan Heng Tseng1,Wen Chao Shen1, Chia-En Huang1, C. -H. Kuo2, Y. -D. Chih2, Chrong Jung Lin1, Ya-Chin King1, “Electron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis”, IEEE International Electron Devices Meeting (IEDM)

35.   Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, and Chrong Jung Lin Shyh-Shyuan Sheu*, Yu-Sheng Chen*, Heng-Yuan Lee*, Frederick T. Chen*, and Ming-Jinn Tsai*, “3-Dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process”, IEEE International Electron Devices Meeting (IEDM)

 

C.         Review Chapter

“Nanocrystal Memories”, Ya-Chin King, Handbook of Nanoceramics and Their Based Nanodevices, Editor: Tseung-Yuen Tseng and H. S. Nalwa, American Scientific Publishers, Valencia, CA, U.S.A. ( 2007).

 

I.     專利

中華民國專利 (ROC Patent)

2005

51.       ROC Patent, No. I237998, 2005, “影像感測單元之操作方法及使用其之影像感測裝置”, by 賴成孝, 金雅琴, 余岳平

52.       ROC Patent, No. I236733, 2005, “製作快閃記憶體元件之方法”, by 謝佳達, 郭迪生, 葉壯格 and林崇榮, 朱文定 and 張傳理

2006

53.       ROC Patent, No. I249947, 2006, “數位式影像感測器及其運作方法”, by 賴成孝, 金雅琴

54.       ROC Patent, No. I264086, 2006, “影像感測器以及影像感測方法”, by 金雅琴, 賴成孝, 林哲毅

2007

55.       ROC Patent, No. I287868, 2007, “單層複晶矽非揮發性記憶體裝置”, by林崇榮, 陳信銘,沈士傑, 金雅琴, and徐清祥

56.       ROC Patent, No. I270076, 2007, “可選擇位元資料修改之快閃記憶胞陣列結構”, by池育德, 曹昇巍, 林崇榮, and王清煌

2008

57.       ROC Patent, No. I292622, 2008, “單層複晶矽非揮發性記憶體的操作方法”, by林崇榮, 陳信銘,沈士傑, 金雅琴, and徐清祥

58.       ROC Patent, No. I299866, 2008, “單層複晶矽非揮發性記憶體的操作方法”, by林崇榮, 陳信銘, 沈士傑, 金雅琴, 徐清祥

59.       ROC Patent, No. I294692, 2008, “NOS非揮發型記憶胞及其操作方法”, by金雅琴, 林崇榮

60.       ROC Patent, No. I295848, 2008, “非揮發性雙位元記憶體及其操作方法”, by金雅琴, 林崇榮

61.       ROC Patent, No. I298933, 2008, “閘極側壁儲存之雙位元非揮發型記憶胞及其操作方法”, by金雅琴, 林崇榮

2009

62.   ROC Patent, No. I312190, 2009, “奈米矽顆粒型架構之影像感測元件”, by 金雅琴, 林崇榮

2010

63.   ROC Patent, No. I324832, 2009, “光感測元件及其製作方法”, by翁健森, 趙志偉, 林崇榮, 金雅琴

 

美國專利(US Patent)

2005

59.       U.S. Patent, No.6842374, 2005, “Method for operating N-channel electrically erasable programmable logic device”, by Lee; Kung-Hong , Hsu; Ching-Hsiang , King; Ya-Chin , Shen; Shih-Jye , Ho; Ming-Chou

60.       U.S. Patent, No. 6855994, 2005, “Multiple-thickness gate oxide formed by oxygen implantation”, by King; Ya-Chin, King; Tsu-Jae, Hu; Chen Ming

61.       U.S. Patent, No. 6902978,2005, “Method of Making the Selection Gate in a Split-Gate Flash EEPROM Cell and Its Structure”, by Chu; Wen-Ting, Yeh; Jack (Chu Pei, TW), Lin; Chrong-Jung (Taipei, TW)

62.       U.S. Patent, No.6838725, 2005, “Step-Shaped Floating Poly-Si Gate to Improve a Gate Coupling Ratio For Flash Memory Application”, by Chrong Jung Lin and Shui-Hung Chen

63.       U.S. Patent, No.6933198, 2005, “Method for Forming Enhanced Areal Density Split Gate Field Effect Transistor Device Array”, by Wen-Ting Chu, Chai-Ta Hsieh, and Chrong Jung Lin

2006

64.       U.S. Patent, No. 7196306, 2006, “Image sensor pixel circuitry with transistors to improve dynamic range”, by King; Ya-Chin, Lai; Cheng-Hsiao, Lin; Che-I

65.       U.S. Patent, No. 6982458, 2006, “Method of Making the Selection Gate in a Split-Gate Flash EEPROM Cell and Its Structure”, by Wen-Ting Chu, Jack Yeh, and Chrong Jung Lin

66.       U.S. Patent, No. 7057228, 2006, “Memory Array with Byte-Alterable Capability”, by Yue-Der Chih, Chrong Jung Lin, Shen-Wei Tsao, and Chin Huang Wang

67.       U.S. Patent, No. 7122857, 2006, “Multi-Level ( 4 state/ 2-bit) Stacked Gate Flash Memory Cell”, by Yue-Der Chih, Chrong Jung Lin, Shui-Hung Chen, and Hsin-Ming Chen

2007

68.     U.S. Patent, No. 7164114, 2007, “Digital pixel sensor with clock count output and operating method thereof ”, by Lai; Cheng-Hsiao, King; Ya-Chin

2009

69.    U.S. Patent, No. 7551494, 2009, “SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD ”, by Lin; Chrong-Jung, Chen; Hsin-Ming, Shen; Shih-Jye, King; Ya-Chin, Hsu; Ching-Hsiang

70.    U.S. Patent, No. 7575948, 2009, “Method for operating photosensitive device ”, by Lin; Chrong-Jung, King; Ya-Chin

71.    U.S. Patent, No.7590005, 2009, “Program and erase methods with substrate transient hot carrier injections in a non-volatile memory”, by Hsu; Tzu Hsuan, Wu; Chao-I, Hsieh; Kuang Yeu, King; Ya-Chin